Optimization of n-channel and p-channel T-FET

In this work, we explore various optimization techniques using bandgap engineering to enhance the performance of tunnel FETs (T-FET) using extensive device simulations. We show that the heterostructure (Si1-γGeγ source or drain) tunnel FET (HT-FET) architecture allows scaling of the device to sub 20 nm gate length regime. N-channel HT-FET is optimized to meet ITRS low standby power and high performance logic technology requirements with 20 nm gate length, for the first time. Novel optimization technique is proposed for p-channel T-FET which results in better subthreshold slope and increased ON current. For optimizing pchannel T-FET, we use a heterostructure with Si1-γGeγ drain. The Ge content and the gate overlap are used as optimization parameters. Comparative study of gate length scaling effects on Si T-FET and HT-FET is done. We show that for sub 20 nm gate lengths, the heterostructure provides an added advantage of reducing short channel effects. We have also explored the possibility of CMOS implementation of HT-FET.